By J. Bhasker,Rakesh Chadha

ISBN-10: 0387938192

ISBN-13: 9780387938196

ISBN-10: 1441947159

ISBN-13: 9781441947154

iming, timing, timing! that's the major trouble of a electronic dressmaker charged with designing a semiconductor chip. what's it, how is it T defined, and the way does one make sure it? The layout workforce of a big electronic layout may well spend months architecting and iterating the layout to accomplish the necessary timing objective. in addition to useful verification, the t- ing closure is the most important milestone which dictates whilst a chip may be - leased to the semiconductor foundry for fabrication. This e-book addresses the timing verification utilizing static timing research for nanometer designs. The publication has originated from decades of our operating within the quarter of timing verification for advanced nanometer designs. we now have stumble upon many layout engineers attempting to research the historical past and diverse elements of static timing research. regrettably, there is not any booklet presently ava- capable that may be utilized by a operating engineer to get accustomed to the - tails of static timing research. The chip designers lack a significant reference for info on timing, that covers the fundamentals to the complex timing veri- cation strategies and techniques.

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Static Timing Analysis for Nanometer Designs: A Practical Approach by J. Bhasker,Rakesh Chadha

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